Computer systems typically include one or more data processing devices (processors) and a main memory system having one or more memory devices (memory modules). Such computer systems often perform self test procedures that determine whether the processors and memory devices are operating properly.
In one type of computer system, a processor initially performs a self test of its own internal components. If the processor passes the self test, the processor tests the memory system. In particular, the processor writes data to and reads data from the memory modules within the memory system to verify that the memory modules can store and provide data correctly. Typically, this processor-performed read/write procedure tests the memory modules in a serial manner. If the memory system passes the test, the computer system enters a normal operating mode.
In another type of computer system, a processor performs a self test of its internal components, and subsequently instructs the memory modules to execute internal self tests, and those self tests are conducted in parallel. Each memory module of the memory system responds by simultaneously running an individual self test utilizing internal error detecting and correcting circuitry (EDC). In this parallel self test procedure, the processor considers the memory system operational if each memory module passes its respective self test. If the processor determines that the memory system is operational, the computer system enters its normal operating mode. A conventional computer system that performs a parallel self test procedure that is similar to that described above is disclosed in U.S. Pat. No. 5,216,672, the entire teachings of which are hereby incorporated by reference.
The parallel self test procedure requires less time to complete than the processor-performed read/write procedure. In particular, the time required to test memory modules using the parallel self test procedure is the time required for one memory module to perform its self test since the memory modules operate in parallel. In contrast, the time required to test memory modules using the processor-performed read/write procedure is the total time required to serially test the memory modules. Furthermore, the internal bandwidth of a memory module is generally greater than the bandwidth of an interconnect between a processor and a memory system. Accordingly, it typically takes less time for a memory module to perform a self test internally than for a processor to test a memory module by performing read/write transactions through the interconnect.